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HCF4089B
BINARY RATE MULTIPLIER
s s
s
s
s s
s s
CASCADABLE IN MULTIPLES OF 4-BITS SET TO "15" INPUT AND "15" DETECT OUTPUT QUIESCENT CURRENT SPECIFIED UP TO 20V STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS 5V, 10V AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B "STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES"
DIP
SOP
ORDER CODES
PACKAGE DIP SOP TUBE HCF4089BEY HCF4089BM1 T&R HCF4089M013TR
DESCRIPTION HCF4089B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages. HCF4089B is a low power 4-bit digital rate multiplier that provides an output pulse rate that is the clock input pulse rate multiplied by 1/16 times the binary input. For example, when the binary input number is 13, ther will be 13 output pulses for every 16 input pulses. HCF4089B has an internal synchronous 4-bit counter, which, together with one of the four
binary inputs bits, produces pulse trains as shown in the timing diagram. If more than one binary input bit is high, the resulting pulse train is a combination of the above separate pulse trains. This device may be used to perform arithmetic operations (add, subtract, divide, raise to a power), solve algebrical and differential equations, generate natural logarithms and trigonometric functions, A/D and D/A conversions, and frequency division.
PIN CONNECTION
September 2002
1/11
HCF4089B
IINPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No 14, 15, 2, 3 5 6 4 1 7 13 12 11 10 9 8 16 SYMBOL A, B, C, D OUT OUT SET TO "15" "15" OUT INHIBIT OUT (CARRY) CLEAR CASCADE INHIBIT IN (CARRY) STROBE CLOCK VSS VDD NAME AND FUNCTION Binary Rate Select Inputs Rate Output Rate Output Set Input Output Inhibit Out (Carry) Clear Input Cascade Inhibit Input (Carry) Strobe Clock Input Negative Supply Voltage Positive Supply Voltage
FUNCTIONAL DIAGRAM
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HCF4089B
TRUTH TABLE
INPUTS Number of Pulses or Input Logic Level D L L L L L L L L H H H H H H H H X X X H L X C L L L L H H H H L L L L H H H H X X X X X X B L L H H L L H H L L H H L L H H X X X X X X A L H L H L H L H L H L H L H L H X X X X X X CLOCK 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 INH IN L L L L L L L L L L L L L L L L H L L L L L STR. L L L L L L L L L L L L L L L L L H L L L L CAS. L L L L L L L L L L L L L L L L L L H L L L CLEAR L L L L L L L L L L L L L L L L L L L H H L SET L L L L L L L L L L L L L L L L L L L L L H OUTPUTS Number of Pulses or Output Logic Level OUT L 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 * L H 16 L L OUT H 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 * H * 16 H H INH OUT 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 H 1 1 H H L "15" OUT 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 * 1 1 L L H
X : Don't Care * : Depends on internal state of counter *: Output same as the first 16 lines of this truth table (depending on values of A, B, C, D)
LOGIC DIAGRAM
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HCF4089B
TIMING CHART
ABSOLUTE MAXIMUM RATINGS
Symbol VDD VI II PD Top Tstg Supply Voltage DC Input Voltage DC Input Current Power Dissipation per Package Power Dissipation per Output Transistor Operating Temperature Storage Temperature Parameter Value -0.5 to +22 -0.5 to VDD + 0.5 10 200 100 -55 to +125 -65 to +150 Unit V V mA mW mW C C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All voltage values are referred to VSS pin voltage.
RECOMMENDED OPERATING CONDITIONS
Symbol VDD VI Top Supply Voltage Input Voltage Operating Temperature Parameter Value 3 to 20 0 to VDD -55 to 125 Unit V V C
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HCF4089B
DC SPECIFICATIONS
Test Condition Symbol Parameter VI (V) 0/5 0/10 0/15 0/20 0/5 0/10 0/15 5/0 10/0 15/0 0.5/4.5 1/9 1.5/13.5 4.5/0.5 9/1 13.5/1.5 2.5 4.6 9.5 13.5 0.4 0.5 1.5 VO (V) |IO| VDD (A) (V) 5 10 15 20 5 10 15 5 10 15 5 10 15 5 10 15 5 5 10 15 5 10 15 18 TA = 25C Min. Typ. 0.04 0.04 0.04 0.08 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 -1.36 -0.44 -1.1 -3.0 0.44 1.1 3.0 -3.2 -1 -2.6 -6.8 1 2.6 6.8 10-5 5 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 3.5 7 11 1.5 3 4 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 Max. 5 10 20 100 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 Value -40 to 85C Min. Max. 150 300 600 3000 4.95 9.95 14.95 0.05 0.05 0.05 -55 to 125C Min. Max. 150 300 600 3000 Unit
IL
Quiescent Current
A
VOH
High Level Output Voltage Low Level Output Voltage High Level Input Voltage Low Level Input Voltage Output Drive Current
VOL
VIH
VIL
IOH
IOL
Output Sink Current Input Leakage Current Input Capacitance
0/5 0/5 0/10 0/15 0/5 0/10 0/15 0/18
<1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1
V
V
V
V
mA
mA
II
Any Input Any Input
0.1
7.5
1
1
A
pF
CI
The Noise Margin for both "1" and "0" level is: 1V min. with VDD =5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V
DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25C, CL = 50pF, RL = 200K, tr = tf = 20 ns)
Test Condition Symbol Parameter VDD (V) 5 10 15 5 10 15 5 10 15 5 10 15 Min. Value (*) Typ. 110 55 45 150 75 60 360 160 110 250 100 75 Max. 220 110 90 300 150 120 720 320 220 500 200 150 ns Unit
tPHL tPLH Propagation Delay Time CLOCK to OUT tPHL tPLH Propagation Delay Time CLOCK or STROBE to OUT tPHL tPLH Propagation Delay Time CLOCK to INHIBIT High Level to Low Level tPHL tPLH Propagation Delay Time LOW Level to HIGH Level
ns
ns
ns
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HCF4089B
Test Condition Symbol Parameter VDD (V) 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 Min.
Value (*) Typ. 380 175 130 300 125 90 90 45 35 160 75 55 330 150 110 100 50 40 2.4 5 7 165 85 50 Max. 760 350 260 600 250 180 180 90 70 320 150 110 660 300 220 200 100 80
Unit
tPHL tPLH Propagation Delay Time CLEAR to OUT tPHL tPLH Propagation Delay Time CLOCK to "9" or "15" OUT tPHL tPLH Propagation Delay Time CASCADE to OUT tPHL tPLH Propagation Delay Time INHIBIT IN to INHIBIT OUT tPHL tPLH Propagation Delay Time SET to OUT tTHL tTLH Transition Time
ns
ns
ns
ns
ns
ns
fCL
Maximum Clock Frequency Clock Pulse Width
tW
1.2 2.5 3.5 330 170 100
MHz
ns 15 15 15
tr, tf
Clock Rise or Fall Time
s
tW
SET or CLEAR pulse Width INHIBIT Input Set-Up Time, High Level to Low Level INHIBIT Input Removal Time Minimum SET Removal Time CLEAR Removal Time
tsetup
tR
tR
tR
160 90 60 100 40 20 240 130 110 150 80 50 60 40 30
80 45 30 50 20 10 120 65 55 75 40 25 30 20 15
ns
ns
ns
ns
ns
(*) Typical temperature coefficient for all VDD value is 0.3 %/C.
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HCF4089B
APPLICATION NOTES For words of more than 4 bits, HCF4089B device may be cascaded in two different modes : an ADD mode and a MULTIPLY mode. TWO HCF4089B'S CASCADED IN THE "ADD" MODE WITH A PRESET NUMBER OF 189
In the ADD mode some of the gaps left by the more significant unit at the count of 15 are filled in by the less significant units. For example, when two units are cascaded in the ADD mode and programmed to 11 and 13, respectively, the more significant unit will have 11 output pulses and the other unit will have 13 output pulses for every 256 input pulses for a total of : 11 13 189 + = 16 256 256
TWO HCF4089B'S CASCADED IN THE "MULTIPLY" MODE FOR MULTIPLICATION OF TWO VARIABLES A AND B WITH LOOP CIRCUIT CONTROL
A B 1 N When the loop stabilities rate R2 = rate R3, thus fclock( * ) = fclock ( * ) therefore N = AB 16 16 16 16
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HCF4089B
TEST CIRCUIT
CL = 50pF or equivalent (includes jig and probe capacitance) RL = 200K RT = ZOUT of pulse generator (typically 50)
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HCF4089B
Plastic DIP-16 (0.25) MECHANICAL DATA
mm. DIM. MIN. a1 B b b1 D E e e3 F I L Z 3.3 1.27 8.5 2.54 17.78 7.1 5.1 0.130 0.050 0.51 0.77 0.5 0.25 20 0.335 0.100 0.700 0.280 0.201 1.65 TYP MAX. MIN. 0.020 0.030 0.020 0.010 0.787 0.065 TYP. MAX. inch
P001C
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HCF4089B
SO-16 MECHANICAL DATA
DIM. A a1 a2 b b1 C c1 D E e e3 F G L M S 3.8 4.6 0.5 9.8 5.8 1.27 8.89 4.0 5.3 1.27 0.62 8 (max.) 0.149 0.181 0.019 10 6.2 0.35 0.19 0.5 45 (typ.) 0.385 0.228 0.050 0.350 0.157 0.208 0.050 0.024 0.393 0.244 0.1 mm. MIN. TYP MAX. 1.75 0.2 1.65 0.46 0.25 0.013 0.007 0.019 0.003 MIN. inch TYP. MAX. 0.068 0.007 0.064 0.018 0.010
PO13H
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HCF4089B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2002 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. (c) http://www.st.com
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